The present invention relates to a multiple-interrupt system, and more particularly to the detection of an abnormal operation caused by interrupt processing in a multiple-interrupt system.
In order to guarantee realtimeness in an embedded system or the like, there is a system configured such that, when there is an interrupt request higher in priority than the priority (level) of interrupt being processed, the interrupt being processed is suspended and the higher-priority interrupt is processed, and after completion of the interrupt processing, the suspended interrupt processing is resumed. The system is a so-called multiple-interrupt system or a system for nesting interrupts according to priority.
There is also a system equipped with a watchdog timer (hereinafter referred to as “WDT”) as hardware for monitoring that the system is operating regardless of whether the system is a multiple-interrupt system.
In an embedded system or the like, the system may not operate normally despite the fact that the WDT has not timed out (expired). There are various causes of abnormal operations, and there are also many abnormal operations associated with interrupt processing. In the case of a multiple-interrupt system, automatic recovery and cause analysis are often made difficult.
An example of the insufficient detection of an abnormal operation is a case where the WDT is reset by a timer interrupt (or by all interrupts) (because there is one WDT in normal systems). In this case, the WDT can only confirm that the CPU (and surrounding H/W) is operating. In other words, the WDT confirms that a peripheral circuit issues an interrupt request and the CPU accepts the request. In this regard, it is not confirmed whether an operation expected by the system is being performed or not.
Japanese Patent Application Publication No. 62-175840 discloses a data processing system for executing multiple processing programs according to the levels in the intervals of execution of a processing program having the highest level (highest execution priority level). In this system, multiple WDTs having overflow values different according to the levels of the processing programs and reset after completion of the execution of corresponding processing programs are provided to detect the occurrence of a failure in the data processing system based on the overflow of any one WDT.
Japanese Patent Application Publication No. 10-275097 discloses a data processing system for executing multiple processing programs in order of priority according to the levels. In this system, multiple WDTs individually corresponding to the respective multiple processing programs are arranged to detect the occurrence of a hang-up of the data processing system based on the overflows of these multiple WDTs.
The data processing system in Japanese Patent Publication No. 62-175840 assumes the execution of the highest-level processing program started by the timer, and does not support interrupt processing between levels lower than the highest level or interrupt processing when multiple programs are assigned to one level. Further, there is no disclosure about the timings of starting the WDTs.
In the data processing system in Japanese Patent Publication No. 10-275097, since the multiple WDTs are not started in parallel, the multiple interrupts different in priority cannot be processed (managed) in parallel.